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CMOS OC-48c Physical Layer/Framer Device - PCstats.com CMOS OC-48c Physical Layer/Framer Device
Mon, May 08 2000 | 4:42PM | PermaLink Feedback?
If any one can explain what this is, please email me :-)

"Implemented entirely in mainstream 0.18 micron / 1.8 volt CMOS technology, the S/UNI-2488 physical layer / framer achieves a typical power consumption of under 3 watts, which sets the standard relative to alternative multi-chip and/or exotic material PHY/framer approaches. The use of mainstream CMOS for high-speed OC-48 systems enables lower power and ease of future silicon integration for next-generation equipment upgrades. The S/UNI-2488 leverages PMC-Sierra's extensive high-speed, CMOS analog design expertise developed previously at OC-3c (155 Mbit/s) and OC- 12c (622 Mbit/s) rates. The OC-48c (2.5 Gbit/s) physical layer front end CRSU and SERDES functions implement analog phase-locked-loop circuit technology that meets Bellcore GR-253 intrinsic jitter specifications as well as meeting jitter tolerance and jitter transfer specifications."
FULL STORY @ Archived from DIMENSION X
http://www.dimensionx.sitehosting.net/NewsWirePost/press006.htm
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