Next generation VIA processor core, codenamed “Esther”, to be produced using IBM’s advanced 90nm SOI, low-k manufacturing technology for higher performance with lower power consumption

Taipei, Taiwan and Las Vegas, USA, 06 January 2004 - VIA Technologies, Inc, a leading innovator and developer of silicon chip technologies and PC platform solutions, today announced the selection of IBM Microelectronics, the world's premier information technology supplier, as its foundry partner for the next generation of VIA processors based on the “Esther” core scheduled for the second half of 2004.

VIA’s decision to partner with IBM was based on the company’s ground breaking silicon manufacturing technologies, such as copper interconnects, silicon-on-insulator (SOI) and low-k dielectric insulation, together with its advanced 90-nanometer (nm) process. These advanced manufacturing technologies are designed to reduce power consumption and allow processor speeds of 2GHz and beyond within the same thermal envelope as current VIA processors.

“We are delighted to be working with IBM, and believe that our combined expertise in processor design and manufacturing will ensure that we continue to produce the world’s smallest and most efficient native x86 processors,” said Wenchi Chen, President and CEO, VIA Technologies, Inc. “VIA processors are spurring the development of exciting new devices in areas such as the connected home and mobile entertainment, and we are confident that our new partnership with IBM will lead to unprecedented innovation in future convergence device markets.”

The transition of from 130nm to the 90nm manufacturing process provides greater scope for power saving and performance enhancements. Decreasing the internal distances traveled by electronic signals within the processor reduces power consumption, while the low-k dielectric technique, introduced by IBM, is a new method of building microchips that can deliver boosts in computing speed and performance of up to a 30 percent by facilitating the faster movement of electronic signals through the chip. Similarly, IBM’s SOI CMOS technology limits transistor leakage, further increasing performance by an estimated 20-35% while reducing power consumption.