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Nehalem, Larrabee and Sandy Bridge |
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| Tue, March 25 2008 | 3:14PM | PermaLink |
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Intel’s discrete graphics product will be built on Intel IA technology with many smaller cores (possibly between 16 to 24, each with 16 in-order threads) and based on the x86 instruction set. Steve Smith confirmed that Larrabee will use a wide SIMD design, but the company hasn't gone into details on the gory architectural details. What we do know though is that it is scalable to teraFLOPS - there's no doubt that some ideas from the Terascale research project will probably be expanded upon in Larrabee.
Smith said that it is designed to be a “programmable x86 machine” with extensions including vector instruction set including memory ops, conditional and integer/arithmetic. Each core has local cache (currently an unspecified amount) in addition to a global cache, along with a texture sampler and a rasteriser option, meaning that it will eventually compete with Nvidia and AMD in the graphics market.
To quote the company, “Intel will have a competitive graphics product [in 2009]”, although we believe that early market launches will be designed for workstation and HPC applications. It will also be built “using Intel’s leading process technology” which we assume to be 45nm and beyond."
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http://www.bit-tech.net/hardware/2008/03/19/intel_talks_nehalem_larrabee_and_32nm/1
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