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In the same workload presented to the conventional memory modules, the threaded modules will require 16 transactions for each 64 Byte transfer, but will combine two parallel hemichannels, thereby achieving full bandwidth. The duration of the burst is 8T (12.5ns), which is long enough to completely mask tRRD at 5T, hence the modules can do seamless back-to-back transactions. On average, 2.5 row activates are necessary within each 30 ns tFAW window, which is less than the limit of four, therefore no wait states need to be inserted and the modules can utilize the full theoretically available bandwidth.
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