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ECC, Scrubbing and Resetting the Clock - PCstats.com ECC, Scrubbing and Resetting the Clock
Tue, July 27 2010 | 5:07PM | PermaLink Feedback?
Read disturb and Over-Erasing are becoming increasingly important factors in the management of data stored in NAND flash-based mass storage devices. In the case of Read Disturb the problem that every read of a page in NAND flash will cause an ever so slight change in the level of programming charge of all other cells in the same block is a definite cause for concern. However, modern SSD/NAND flash controllers are, at least in theory, perfectly capable of coping with this situation. That is, typically, it is not a single page that is read within a block or else, recurrent accesses will eventually hit a different page in any block subjected to high read activity. In this case ECC algorithms along with monitoring of the bit error rate (BER) will provide an indicator of the potential deterioration of data integrity in a given block or other portion of the array and signal the controller to recuperate the existing data before a point of no return is reached in order to store the data in a different block. At that point, the entire cycle starts all over since the “read disturb clock” is reset to zero with every program/erase cycle. In the final analysis, even though Read Disturb is becoming a problem, modern controllers are, at least in theory, perfectly capable of coping with it by using the bit error rate at any data access as indicator for deterioration of data integrity. If the bit error rate increases above a predetermined value, then the controller will know that the specific set of data is deteriorating as a function of read disturb, stress-induced leakage current or any other factor like cosmic rays or alpha particle and react by taking the appropriate countermeasures in the form of “refreshing” the data by copying them to a different location after verifying the integrity and correcting apparent errors using ECC algorithms.
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