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AMD AthlonT Processor Performance-Enhancing
Date: Sunday June 04, 2000
Category: Press Release
Manufacturer Link: AMD Discus -- BBS
Enabling an Innovative Full-Speed On-die Cache for High-Performance x86 Processors


AMD AthlonT Processor Performance-Enhancing

Cache Memory


Enabling an Innovative Full-Speed On-die Cache

for High-Performance x86 Processors



One AMD Place

Sunnyvale, CA 94088

Introduction: The AMD AthlonT Processor with

Performance-Enhancing Cache Memory


At its introduction, the AMD AthlonT processor marked the arrival of the world's first seventh-generation microarchitecture and in doing so set the performance standard for x86 processors. Among the processor's now award-winning architectural features are a revolutionary 200MHz, 1.6Gbytes/sec system bus, a fully pipelined, superscalar floating point engine, and an enhanced version of AMD's 3DNow!T technology. Additionally, the processor offers 128K of L1 cache-four times the L1 cache of competing x86 processors-along with a 512K external backside L2 cache running at up to half the speed of the processor core.

With new versions of the AMD Athlon processor, however, AMD has sought to improve overall system performance by integrating the processor's L2 cache directly onto the processor die. This white paper explains the benefits of utilizing an AMD Athlon processor with on-chip, performance-enhancing cache memory.

The AMD Athlon processor with performance-enhancing cache memory boasts three times the full-speed on-die cache of previous AMD Athlon processors.  It features 128K of L1 cache plus 256K of full-speed, on-chip cache for a total internal system cache of 384K. 

Integration of the L2 cache onto the die eliminates the need for expensive, high-performance L2 cache SRAM. Moreover, on-die L2 cache enables the L2 cache speed to scale with the processor speed, thereby enabling a more substantial level of performance across a broad range of standard and memory-intensive applications.

With the AMD Athlon processor's migration to 0.18-micron process technology completed, the integrated cache design does not significantly change the size of the die. The advanced 0.18-micron manufacturing process enables smaller transistor sizes in comparison to the 0.25-micron process. Therefore, the space penalty for the integration of the L2 cache is mild, as the L2 cache accounts for only 20% of the entire processor die.  The AMD Athlon processor's 37-million-transistor-die is now ~120 mm2.


Improved L2 Cache Efficiency through Lower Latency, Increased Bandwidth and Greater Associativity


Integrating the L2 cache onto the processor die significantly lowers the hit latency, as it takes much less time to move data across the die than to read it from an external SRAM. The lower the latency, the shorter the response time required for receipt of requested data. The AMD Athlon processor with performance-enhancing cache memory delivers more than 45% lower latency compared to previous AMD Athlon processors, dropping from 21 cycles to 11.

Cache Bandwidth

The increase in cache speed enabled by integration of the L2 cache onto the processor die increases L2 cache bandwidth by 300% over previous AMD Athlon processors. Higher bandwidths allow the processor to work on more data over time.

Set Associativity

The new AMD Athlon processor's 16-way set associative cache is eight times more associative than previous AMD Athlon processors featuring a 2-way set associative cache.  Increasing the set associativity significantly increases the hit rate.  A hit occurs when the processor successfully finds the data that it is looking for in cache memory.  If the data is not found in cache memory, the processor must search for the data in main memory.  Because main memory is limited by its lower speeds-currently no faster than 133MHz-and is serviced by the front-side system bus, cache hits significantly decrease latencies.

The Benefits of Exclusive Cache Architecture

The new AMD Athlon processor with performance-enhancing cache memory features an exclusive cache architecture as opposed to an inclusive cache architecture. An inclusive cache architecture requires the L2 cache to duplicate every cache block held by the processor's L1 cache.  In other words, for every cache block in an inclusive cache architecture's L1 cache, the L2 cache must contain the same redundant data, thereby decreasing the amount of L2 cache available for new information. An exclusive cache architecture, on the other hand, contains only victim or copy-back cache blocks to be written back to the memory sub-system.  This provides a full 256KB of dedicated L2 cache and 128KB of L1 cache for a total dedicated data space of 384KB.


Redundant Columns

To improve yield, the cache includes redundant columns.  Redundant columns improve yield by allowing defective memory cells to be excluded from the cache without sacrificing the overall integrity of the cache.  The entire array can be quickly validated during manufacturing using a built-in self test (BIST).


Fill Buffers, Bus Queue Entries and Write Back Buffers

The new AMD Athlon processor, like previous AMD Athlon processors, includes eight fill buffers, eight bus queue entries, and eight write back buffers. Intel's Pentiumr III processor only has six fill buffers, eight bus queue entries, and four write back buffers.  The more buffers that are dedicated to holding data for the microprocessor to process, the less likely the processor will stall while waiting for data to be delivered to the processor.  More buffers also make it more likely that data can be placed into the buffers for execution. These design elements allow the new AMD Athlon processor to have a sustainable bus bandwidth of 1.6 GB/s-or 85% of peak capacity.


Summary: Enabling Improved Performance Across Standard

and Memory-Intensive Applications

The AMD Athlon processor's cache architecture is the first to incorporate a system-based MOESI (Modify, Owner, Exclusive, Shared, Invalid) cache control protocol for x86 multiprocessing platforms. Since the system logic manages memory coherency throughout the system by specifying all cache state transitions, either using a MESI or MOESI cache coherency protocol, and by filtering out unnecessary processor snoops, AMD Athlon processors are designed to deliver exceptional performance in both uniprocessor and multiprocessor system configurations. The AMD Athlon processor cache architecture also supports error correction code (ECC) protection, which is a required feature for high reliability of business desktop systems, workstations, and servers. Thus, the AMD Athlon processor's cache architecture provides the features required for high-performance computing from desktop to server configurations.


AMD Overview

AMD (NYSE: AMD) is a global supplier of integrated circuits for the personal and networked computer and communications markets. AMD produces processors, flash memories, and products for communications and networking applications. The world's second-leading supplier of Windowsr compatible processors, AMD has shipped more than 120 million x86 microprocessors, including more than 90 million Windows compatible CPUs. Founded in 1969 and based in Sunnyvale, California, AMD has sales and marketing offices worldwide and manufacturing facilities in Sunnyvale; Austin, Texas; Dresden, Germany; Bangkok, Thailand; Penang, Malaysia; Singapore; and Aizu-Wakamatsu, Japan. AMD had revenues of $2.8 billion in 1999.

Cautionary Statement

This release contains forward-looking statements, which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally preceded by words such as "expects," "plans," "believes," "anticipates," or "intends." Investors are cautioned that all forward-looking statements in this document involve risks and uncertainty that could cause actual results to differ materially from current expectations. Forward-looking statements in this document about the AMD Athlon processor involve the risk that the AMD Athlon system bus will not support the requirements of next-generation system platforms; that AMD may not be successful in developing an infrastructure to support the processor; that third parties may not provide peripherals or the infrastructure to support the processor and the processor's system bus; and that the processor will not achieve customer and market acceptance. We urge investors to review in detail the risks and uncertainties in the company's Securities and Exchange Commission filings, including the most recently filed Form-10K.


AMD, the AMD logo, AMD Athlon and combinations thereof, and 3DNow! are trademarks of Advanced Micro Devices, Inc. Windows is a registered trademark of Microsoft Corporation. Pentium is a registered trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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