Fujitsu is developing new products for the U.S. and
European markets, which are being built to 1394 and OHCI Revision 1.0 (or
higher) specifications. Supporting S400 data rates, these products address
host and device applications. This includes PC motherboards, add-in cards,
printers, scanners, videoconference cameras, set-top boxes, and storage
subsystems. Also under development are 800 Mb stand-alone PHY products.
The MB86613 is a 3-port OHCI controller for PC
applications, it includes many recently added OHCI and 1394 features, such
as Fairness Control and Physical Upper Bound registers, Fly-By
Arbitration, Suspend/Resume, Ping Packet, and Second Cycle Limit.
To address peripheral applications, Fujitsu's
MB86614 is a low-cost two-port, S400 device for printers, scanners,
Fujitsu adopted a 1394 integrated circuit design
program on the principle that 1394 is to be the universal interface
for a broad variety of applications that will cross over the traditional
boundary between computer and consumer markets. For this vision to be
realized, the cost of implementing the 1394 must be driven down so it is
comparable to the application-specific interfaces it is designed to
replace. At the same time, 1394 must maintain interoperability and
compliance with standards that are still evolving.
Fujitsu understands these challenges and is developing
silicon to meet the disparate needs of this diverse application base. We
are targeting specific application segments, identifying the unique
requirements, and integrating functions that are presently processed in
the software stack. Conversely, we are conscious of the effects of
over-integration that can translate into excessive cost, reduced
flexibility, and increased power consumption.
The first Fujitsu 1394 IC implementations were developed
primarily for the Japanese consumer product marketplace. These products,
the MB86611 and MB86612, were designed to the 1394-1995
specification for S100 data rates. The cornerstone of the Fujitsu 1394 LSI
design has been the integration of the complete PHY, which includes
transceivers, PLL, node ID, and arbitration logic, with upper-level LINK
functions into a single 3.3-volt integrated circuit. In addition to LINK
and PHY logic, these devices offer additional processing power for
performing higher-level functions. Time-stamp processing and frame pulse
regeneration for DVC and DVB (MPEG) protocols are two such functions.
Without hardware support, these functions would be executed more slowly by